A connection between a conductive region, e.g. an impurity diffusion layer in a semiconductor substrate or a lower level wiring layer, and an upper level wiring layer through a contact hole formed in an interlayer insulating film is an important technique in manufacturing semiconductor devices. Recently, the fabrication of extremely complex, high-density integrated circuits has been made possible through an advance in integrated circuit fabrication technology. This advance in integrated circuit fabrication technology has scaled devices down toward DRAMs in the gigabit range, which have feature sizes of less than 0.15 .mu.m. In the case of a memory device with an integration density as high as in the gigabits, contact holes inevitably require a high aspect ratio, i.e., a smaller area compared to their depth.
As the aspect ratio of a contact hole increases, however, so too does its contact resistance. To reduce the contact resistance, an ion implanting process is often carried out on the bottom of the contact hole following the formation of the contact hole.
This conventional method for forming a contact is depicted in FIGS. 1A to 1C, which illustrate the process flow in a cross-sectional view. Referring to FIG. 1A, a device isolation layer 12 is formed over a p-type semiconductor substrate 10. An N.sup.+ type impurity diffusion layer 14 is then formed in the p-type semiconductor substrate 10, and an interlayer dielectric layer 16 is formed over the semiconductor substrate 10. A contact hole 18 is then opened in the interlayer dielectric layer 16 to expose a portion of the impurity diffusion layer 14.
Referring to FIG. 1B, in order to improve the contact resistance of this contact hole, impurity ions are implanted into the exposed impurity diffusion layer 14. As is well known, this ions implantation is provided to serve the dual purpose of preventing p-n junction leakage and suppressing any increase in contact resistance. Such an increase in contact resistance may result from substrate damage and the consumption of the impurity diffusion layer caused by over-etching due to contact hole misalignment.
Referring to FIG. 1C, a refractory metal layer 20 is deposited in the contact hole and over the interlayer dielectric layer 16. A portion of refractory metal layer 20 that contacts the exposed substrate 10 and impurity diffusion layer 14 is then transformed into a silicide layer 22 by an annealing process. A barrier metal layer 24 is then deposited in the contact hole and over the refractory metal layer 20. Finally, the remainder of the contact hole is filled with a wiring metal 26, which is patterned, along with the refractory metal layer 20 and the barrier metal layer 24 to form a multilayer metal plug.
The annealing is carried out to out-diffuse implanted impurity ions from the impurity diffusion layer 14 into the silicide layer 22 and the portion of the semiconductor substrate 10 initially in contact with the refractory metal layer 20.
It is noted that the ion implantation is carried out with a high dose of more than 1.times.10.sup.15 cm.sup.-2 under an implantation angle that is substantially a right angle with respect to the substrate, i.e., with a tilt of about 0.degree., because of the high aspect ratio of the contact holes. As a result, the actual impurity concentration depth profile is significantly different from a desired concentration depth profile.
FIG. 2 shows an impurity concentration profile in the silicon substrate after impurity ions are implanted according to this conventional method for forming a contact. As seen in FIG. 2, the actual impurity concentration depth profile 2 has a deep tail portion beyond the critical depth as compared a to desired concentration depth profile 1. This makes if difficult to form a shallow junction and consequently aggravates the short channel effect and increases the channelling effect. Furthermore, substrate damage caused by contact over-etching and point defects caused by ion implanting can cause a silicon dislocation loop at the depletion region of the p-n junction region. An example of such a silicon dislocation loop "A" is depicted in FIG. 3A, which is a vertical XTEM (X-transmission electron microscopy) micrograph. FIG. 3B is a planar SEM (scanning electron microscopy) of a semiconductor substrate having a defect "B" near the edge portion of an interfacing region between an active region and a device isolation region.
In reverse bias, the presence of a silicon dislocation significantly increases the leakage current of the p-n junction by a magnitude of about 10.sup.6, as compared to a normal junction leakage. This increase in the leakage current results in an unacceptable increase in the standby current of the device.